IBM's 0.7nm chip gives Moore's Law another decade—by stacking transistors
ibm revealed a nanostack chip architecture that stacks transistors vertically to boost density 50% and efficiency 70%. this breakthrough could extend hardware scaling limits for ai data centers.
ibm has developed a new vertical stacking architecture called nanostack, fabricating transistors in two layers to fit 100 billion transistors on a fingernail-sized chip. this method bypasses quantum scaling limits to deliver 50% more speed and 70% greater energy efficiency compared to ibm's previous generation. the technology is expected to reach data centers within a decade, crucially impacting the energy footprint of ai training and inference workloads. as intel, samsung, and tsmc pursue similar cfdet approaches, ibm's staggered layer design simplifies wiring and accelerates the timeline for 3d chip manufacturing. this roadmap extension ensures hardware continues to pace with the exponential compute demands of future ai models.